1. Field of the Invention
The present invention relates generally electronic device communication.
2. Description of the Related Art
In modern computing systems, multi-byte values are conventionally stored in either a big endian format or a little endian format. Also, it is generally required that a particular format be applied consistently to ensure compatibility between various components of the computing system. The big endian and little endian formats and the necessity for their consistent application is described below with respect to FIGS. 1A through 1C.
FIG. 1A is an illustration showing an exemplary sequence of bytes to be used as a basis for describing a big endian format and a little endian format. Byte 0 includes bits 0 through 7. Byte 1 includes bits 8 through 15. Byte 2 includes bits 16 through 23. Byte 3 includes bits 24 through 31. For discussion purposes, Byte 3 is defined to be the most significant byte (MSB), and Byte 0 is defined to be the lease significant byte (LSB).
FIG. 1B is an illustration showing the sequence of bytes of FIG. 1A stored in contiguous memory locations in accordance with the big endian format. The big endian format requires the sequence of bytes to be stored in consecutive order with the MSB, Byte 3 in the present example, being stored in the lowest memory location relative to the other bytes in the sequence. The lowest memory location is identified as “Base Address.” The next three higher memory locations are identified in increasing order as “Base Address+1”, “Base Address+2”, and “Base Address+3.” The big endian format also requires the sequence of bytes to be transmitted in consecutive order with the MSB being transmitted first. Thus, in the big endian format as shown in FIG. 1B, the sequence of bytes are transmitted in consecutive order from the “Base Address” to the “Base Address+3.” It will be apparent to those skilled in the art that the Serial Attached SCSI (SAS) protocol utilizes the big endian format.
FIG. 1C is an illustration showing the sequence of bytes of FIG. 1A stored in contiguous memory locations in accordance with the little endian format. The little endian format requires the sequence of bytes to be stored in consecutive order with the LSB, Byte 0 in the present example, being stored in the lowest memory location relative to the other bytes in the sequence. Again, the lowest memory location is identified as “Base Address”, and the next three higher memory locations are identified in increasing order as “Base Address+1”, “Base Address+2”, and “Base Address+3.” The little endian format also requires the sequence of bytes to be transmitted in consecutive order with the LSB being transmitted first. Thus, in the little endian format as shown in FIG. 1C, the sequence of bytes are transmitted in consecutive order from the “Base Address” to the “Base Address+3.” It will be apparent to those skilled in the art that the Serial ATA (SATA) protocol utilizes the little endian format.
Through comparison of the big endian format in FIG. 1B and the little endian format in FIG. 1C it is apparent that the big endian and little endian formats are incompatible with each other. Essentially, the big endian and little endian formats are backwards with respect to each other. Thus, it is difficult to efficiently define a device that is capable of interfacing and operating with both the big endian and the little endian formats. A conventional approach for defining a device that is compliant with both the big endian and the little endian formats (i.e., the SAS and SATA protocols) has required the implementation of two independent data paths and two independent codes sets for controlling the data paths. Thus, the conventional approach has suffered from inefficient duplication of essentially equivalent circuitry components and associated code sets to support each of the independent data paths.
In view of the foregoing, a solution is needed for enabling a single device to communicate with both SAS and SATA protocol devices, i.e., both big endian and little endian devices, respectively, without requiring inefficient duplication of essentially equivalent circuitry components and associated code sets.